1. Technical Field
The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit.
2. Description of Related Art
Semiconductor integrated circuits comprise the majority of electronic circuits in computers and other digital electronic products. Present integrated circuits may contain millions of transistors and may be configured, for example, as a central processing unit (CPU), arithmetic logic unit (ALU), random access memory (RAM), programmable logic array (PLA), application specific integrated circuit (ASIC), or digital signal processor (DSP). Both sophistication and speed of operation of these integrated circuits have rapidly increased because of improvements in integrated circuit manufacturing technologies resulting in smaller and faster devices.
In complex digital integrated circuits, a clock control signal is normally required to operate multi-state clocked logic circuits, such as the aforementioned CPU, ALU, RAM, PLA, ASIC, and DSP integrated circuits. The clock control signal is distributed throughout the integrated circuit to clocked logic circuits contained therein. Multiple clock control signals may be desired, or required, depending on the functionality of the integrated circuit.
Design of complex integrated circuits is accomplished by computer simulation which allows an integrated circuit designer to easily implement and test the design before committing it to silicon. In designing the integrated circuit layout by computer, one of the requirements is to distribute the aforementioned clock control signal. FIG. 1 illustrates the distribution of a clock control signal in an integrated circuit. As shown in FIG. 1, centralized clock control circuit 102 routes clock control signal 104 though staging latches 106 to clocked logic circuits 108. Clock control signal 104 from centralized clock control circuit 102 is routed by means of a main trunk that feeds staging latches 106 that in turn feeds tributaries. The tributaries in turn drive clocked logic circuits 108 that require clock control signal 104. Clock distribution technology utilizes a main trunk with tributaries branching out from the main trunk as needed for connection to clocked logic circuits 108 within the integrated circuit.
Depending on the loading requirements of the integrated circuit logic, active device buffer circuits, commonly called local clock buffers, are used to drive latches within the clocked logic circuit. FIG. 2 illustrates the distribution of a clock control signal within a clocked logic circuit. As shown in FIG. 2, clock control signal 202 is fed to staging latch 204 which in turn feeds clocked logic circuits 206. As stated above, within clocked logic circuits 206 there may be one or more local clock buffers (LCBs) 208. However, when clocked logic circuits 206 contain a large number of LCBs, it may be difficult to construct a signal distribution network which can drive clock control signal 202 to each of the LCBs at a high frequency, indicated by point 210.
That is, all electronic circuit loads have resistance, inductance, and capacitance inherent with the physical structure of the integrated circuit. Integrated circuit devices have predominately resistance and capacitance. The resistance “R” and capacitance “C” create an RC time constant delay to a fast rising edge square wave, such as a clock control signal. Excessive delays in the clock control signals can produce unpredictable behavior by the LCBs. Reliable operation of clocked logic circuits within an integrated circuit depends upon the LCBs behaving properly. If a clock control signal is delayed, the clocked logic circuit may not function properly, potentially causing system instability.
One current solution involves restructuring of the logic in order to reduce the clocked logic circuit into multiple clocked logic circuits, each containing a smaller number of logic devices. This solution is undesirable since it may force the design to be partitioned in a manner which is substantially non-optimal. Another solution is to implement custom-designed distribution network which has smaller propagation delays than that produced by the logic synthesis tool. This is undesirable because it requires manual intervention for a clocked logic circuit which is intended to be implemented purely thru automated design tools.